DM6446 Evaluation Board including: software source code, electronic schematic (circuit diagram), PCB layout and Gerber files. All of these resources allow developers to build the final product with the TMS320DM6441, TMS320DM6443 and TMS320DM6446 digital media processors.
DM6446 EVM Evaluation Board consists of two boards connected. One board contains the DM6446 processor, memory, flash, IDE, JTAG and ethernet interface. The other board is called the expansion board and provides interfaces.
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The TMS320DM6446 (also refer to as the DM6446) make full use of the TI DaVinci ™ technology, to meet the network application of encoding and decoding media processing requirements, a new generation of embedded devices.
The DM6446 can be the OEM and ODM products to market quickly with the strong support of the operating system, a richer user interface, high performance and long battery life, the greatest degree of flexibility through a fully integrated mixed processor solution program.
The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem, the VPSS Subsystem, and a majority of the peripherals and external memories. The ARM Subsystem includes the following features:
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose icroprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
· ARM926EJ -S integer core
· CP15 system control coprocessor
· Memory Management Unit (MMU)
· Separate instruction and data Caches
· Write buffer
· Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
· Separate instruction and data AHB bus interfaces
· Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
DM6446 ARM and DSP integration features are as follows:
· DSP visibility from ARM’s memory map, see the Memory Map section for details
· Boot Modes for DSP - see the Device Configurations section for details
· ARM control of DSP boot / reset - see the Device Configurations section for details
· ARM control of DSP isolation and powerdown / powerup - see the Device Configurations section
· ARM & DSP Interrupts - see the Interrupts section
The ARM9 has access to all of the peripherals on the DM6446 device with the exception of the VICP.
The DSP Subsystem includes the following features:
· C64X+ DSP CPU
· 32KB L1 Program (L1P)/Cache (up to 32KB)
· 80KB L1 Data (L1D)/Cache (up to 32KB)
· 64KB Unified Mapped RAM/Cache (L2)
· Little endian
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilites (including a complex multiply). There is also support for Galois field mutiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a C64X+ DSP CPU Description pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.
Other new features include:
SPLOOP -A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Futhermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions -The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+ compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
•
Instruction Set Enhancement -As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
•
Exceptions Handling -Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
•
Privilege -Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
• Time-Stamp Counter -Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
Its performance 4.752 billion instructions per second (MIPS's) at a clock frequency of 594 MHz C64x + core offers solutions to high-performance DSP programming challenges. DSP core business has the flexibility of the numerical ability of high-speed controller and the processor array. Is the C64x + DSP core processor has 64 general-purpose registers and 32-bit word length of 8 highly independent functional units, two 32-bit multiplier is the result and 6 ALU (ALUs). Eight functional units include instructions to accelerate the performance of video and imaging applications. DSP core can produce four 16-bit multiply accumulate (MACs) per cycle a total of 2,376,000,000 per second mutual aid (MMAC doubled), or eight 8-bit for each mutual aid double the 4752 MMAC total cycle. For more details of the C64x + DSP series, please refer to TMS320C64x/C64x + DSP's CPU and Instruction Set Reference Guide (literature number SPRU732).
The DM6446 also has application-specific hardware logic, memory and other chip-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses two-level cache architecture. First-class program cache (L1P) is a 256K bit direct mapped cache and a data cache (L1D) is a 640K-bit 2-way set-associative cache. 2 memory / cache (II) includes a 512K-bit memory space is shared program and data space. Secondary memory can be configured as mapped memory, cache, or a combination of the two.
The peripheral set includes: 2 configurable video ports; 10/100 Mb / s Ethernet MAC (EMAC) of the management data input / output (MDIO) module; an inter-integrated circuit (I2C interface) Total line interface, an audio serial port (ASP) of; 2 64-bit general purpose timers each configured as two independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pin general-purpose input / output (GPIO) with programmable interrupt / event generation modes, multiplexed with other peripherals; 3 UART hardware handshake support a UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: asynchronous External Memory Interface (EMIFA interface) slow memory / peripherals, and a higher speed synchronous memory interface for DDR2.
The DM6446 device includes a video processing subsystem (VPSS) with two configurable video / imaging peripherals: 1 Video Processing Front End (VPFE) input for video capture, a video processing back-end (VPBE) output with imaging coprocessing device (VICP) used for display.
Video processing front-end (VPFE) by a CCD controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White balance / Focus Module (H3A) and zoom. The City Contemporary Dance Company to connect to common video decoders, CMOS sensors, and charge-coupled devices (CCDs). The Previewer is a real-time image processing engine, the need for raw materials, imaging data from a CMOS sensor or CCD and the conversion from a RGB Bayer pattern to YUV422. Histogram and H3A modules provide statistical information on the original color data used by the DM6446. Zoom image data received separate horizontal and vertical adjustment 1/4x 4-fold increase from the 256 / n, which n is between 64 and 1024.
Video processing back-end (VPBE) screen consisting of the engine (OSD) and a video encoder (VENC). The OSD engine capable of handling two separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window 1 attribute window allowing up to eight levels of alpha mixed. The simulation VENC four DAC, running on the 54 MHz to provide a means of composite NTSC / PAL video, S-Video, and / or component video output. The VENC also provides up to 24-bit digital output interface, RGB888 devices. 8/16-bit BT.656 digital output to output and / or CCIR.601 separate horizontal and vertical sync.
In the Ethernet media access controller (EMAC) provides an efficient interface between the processor and DM644X microcontroller core network. The DM6446 EMAC support 10Base - T and 100 trillion, Texas, or 10 transfers / sec (Mbps) and 100 Mbps in both half-or full-duplex mode, the hardware flow control and quality of service ( QoS) support.
In the management data input / output (MDIO) module continuously investigate all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once candidates have been selected for the physical micro-controller, the MDIO module transparently link state monitoring of their reading of the PHY status register. Link change events are stored in the MDIO module and can choose to interrupt the microprocessor, microcontroller, in order to investigate the status of the contact equipment, and continuously performing costly MDIO access.
The interface, I2C bus and SPI interface, USB2.0 interface, and allows easy DM6446 port VLYNQ control peripherals and / or with the host processor. The DM6446 also provides support for multimedia card MMC / SD, with the support of SDIO.
Of the DM6446 also includes a video / imaging coprocessor (VICP) to uninstall a number of video and image processing tasks of the DSP core, making more DSP MIPS common video and imaging algorithms. For more information about the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.
And provided a wealth of peripherals to control external peripheral devices and communication with external processors. For more information, for each peripheral, see the relevant sections in this document and the associated peripheral reference guide.
The DM6446 has a complete set of development tools are ARM and DSP. These include C compilers, digital signal processing to optimize the General Assembly to simplify programming and scheduling, and visibility Windows ™ debugger interface source code.
Concluded that the TI, because it is the most powerful video processing enterprises in the high-end video processing, is almost a dominance of TI. DM642 is an epoch-making things, just as was the emergence of artillery, DM642 a launch, it is the strongest of the doomed. Indeed, whether it is from the front, back, or DSP processing power, or technical support, or related to the promotion, TI will make every effort, of course, TI is also fully enjoy the fruits of the DM642.
However, DM642 or defective, not only means the chip design defects, there are deficiencies in the application, it is the largest Mingmen DM642: Not suitable for single-chip system. Although, TI The initial thinking is so compatible with DM642 coprocessor, and a single processor, but, after all, unable to.
This directly led to the birth of Davinci platform, although TI by Davinci is not the epoch-making product promotion, but only a combination of products. 1, Davinci structure is not up-to-date, as early as the DM270 and DM320 above, ARM + DSP is the framework; 2, Davinci internal DSP and ARM is not new, are from the previous generation of products developed from.
Davinci is not epoch-making product, but it will also bring to the video revolution, so the manufacturer ARM and the DSP will be a strong impact, at present, because the supplier has not yet Davinci, but also can not see beyond the scenes, on the Currently, those who present with ARM + DSP framework for manufacturers to make products, if the conditions are right, it is estimated that more than half will switch to the Davinci.
There are two sides of anything, Davinci also have weaknesses, that is, integration is too high, facing the opponent too much, can it be a smooth tight encirclement, still unknown. TI originally focused only on DSP, ARM manufacturers focused only on ARM, we can cooperate with each other, promote each other, and now, TI even ARM are robbed of their jobs, Davinci and the development will be the same as the smooth development of DM642, is a big unknown .
Davinci There is also a not very convenient place that is: the external voltage is 1.8V, instead of the traditional 3.3V, so the hardware design engineers should have realized this is what kind of problem.
As several of the issues raised Moderator, I think it is necessary to say a few words:
1, DM6443 and DM6446 video front-end difference is, at present, we have assessed the results of it is: both the DM6443 or DM6446 lot better than DM642, not have to worry about the problem of lack of capacity to pay attention to algorithm optimization;
2, TI provides codec algorithm Davinci only DEMO version, not the product version, the algorithm is to optimize the money, which is TI's strategy has always been. TI will not damage the interests of third parties, TI is able to achieve such a large, third-party credit, on the contrary, TI is also developing a third party. TI Asia's performance this year should be doubled, there is no third party, how to double?
3, there is nothing wrong with Linux operating system, which is the main trend, and Linux running on ARM just above, which is the current hardware and software engineers, should be a good news, at least we do not have a non-mainstream BIOS;
4, has just said, TI's high level of integration has the potential to become the biggest bottleneck of the development of it, it is necessary to the issue of Dialectical View.
Mr. Zheng Xiaolong is responsible for Texas Instruments (TI) of the DSP in the China market and sales operations. He joined TI in 1996 to China as a technology engineer, has been involved in supporting a large number of DSP and related projects. Since 1998, he transferred to sales and marketing departments, engaged in many large customer support operations. In 2000, he conducted a large number of DSP products and solutions to promote the work, especially in emerging markets based on the development of DSP. Over the years he continued in all major electronic media on the development trend of the DSP technology of the article.
TI before adding that he has long been engaged in digital communications systems and software and hardware design of products and applications in the DSP has accumulated some experience. In 1989 he received bachelor's degree in electrical engineering in Tsinghua University.
First of all, Da Vinci TI has introduced two products, both a TMS320DM6443, a TMS320DM6446. First we need to know is, both chips are single-chip SoC system, the characteristics of these two chips is not only digital media processor is the DSP and CPU, combined with digital media, there is still a rich interface, which is a processor platform. The TI chip in the introduction of Da Vinci series, we introduced is not only a platform, there is a series of software. Especially want to emphasize is that this software is a production, test and optimize the software open.
In the dissemination process, a lot of this platform is optimized for multimedia codecs, as well as platform suite, customers can choose according to needs to be done. Support this process also needs a strong support system, we have the support of Linux platform. In addition, the combination of the industry's API, there are multi-media framework, we hope to provide a complete digital media processing software systems.
The third part, in order to enable customers to develop faster and digital media software and systems products, we have called DVEVM (Digital Video Evaluation Board), the core is based on the chip TMS320DM6446. In DVEVM, the integrated montaVISTA integrated software, the industry's implementation of its Linux operating system is very representative.
Leonardo da Vinci, through which we have put forward these two chips, the benefits to users is clear, first of all in favor of customers innovative products, they can be very flexible manner, based on DaVinci digital media processors, a products, can make their products unique.
Customers in the development process of digital media can improve the efficiency of customer's development, to shorten the development cycle. This is why Da Vinci is provide us with the process of the chip, the software has been production tested. Customers can save months of development time.
The overall performance of the system have greatly improved, but also can effectively reduce system costs, use of IP technology, this system can reduce product costs by 50%.
You may think of the understanding of digital media products is more and more, digital media products, including video phone, digital set-top boxes, digital surveillance product type and so on. The past is basically the product development process is based on a number of ways, one is the emphasis on targeted chip, the chip can choose to have it is a special type of chip design. For example, it is for some applications, there is a specific target application. The characteristics of the two chips may be used for products is faster, but less flexibility in some products. For example, there are some changes in standards, adding new features, product characteristics of such areas will be subject to some restrictions to a large extent. Although it may lower the price, but that should not be overlooked here is that both the ASIC or ASSP chip development cycle will be relatively long.
Another application is the use of software programmable approach, the traditional CPU, DSP, there are hardware programmable FPGA. The use of these three chips, an increase of the flexibility of products to a large extent. But it will involve a lot of software, whether it is using software-programmable or programmable hardware will use the flexibility of software innovation. Manufacturers spent a lot of energy, consider how to enable both innovation and flexibility of this platform and products can be improved. For example, products from the left side of the right products to the mobile, there are a number of innovative mobile, for example, DM642, in the world, there will be a lot of applications, in fact, this is the result of a mobile. There are digital cameras like the D270 is for such a mobile product. End of the day we reached the location of this, and that is our platform for the introduction of Da Vinci.
Da Vinci platform ASIC and ASSP with high system efficiency characteristics, at the same time, strong CPU, DSP innovative flexibility. Therefore, the use of da Vinci to design a product, it can be a software programmable flexibility, is an open, customers can have a lot of room for development, while the final products are well targeted. For the future of the digital media market demands a higher price, then have the advantage of Leonardo da Vinci.
Another point we would like to emphasize is that the Da Vinci platform is actually a fusion product, TI combines DSP technology and software technology.
The Da Vinci platform is a very important point is that a strong capacity for innovation. We give an example, for instance, a factory to develop three types of products, a media player, a media player with the communication function, the other one is the broadcast, communications and recording products. Development in the past, we inevitably use the software very complicated, (slide) Here you can see the media codecs, as well as use Linux, API application interface, there are a number of simulations, but also there are some software products, this is a very important factor. In the broadcast and communication with one Ethernet interface, MP3, H.263, such as broadcast, communications and recording requirements, there are MP3 codec. Application of the basic 6443, and broadcast and communications for 6443 can be used, while for broadcast, communications and recording can be used to 6446. Players can be divided into two parts, part of the Da Vinci platform software and hardware implementation. On the other hand, OEM manufacturers, can improve the value of their products. This is to provide them with value-added space. DaVinci technology is actually able to offer our customers more innovative space technologies. This is also for this reason we named Da Vinci platform and technical reasons, in the hope that our customers will be able to become a master of creativity.
From the hardware point of view, how we achieved? This might be a more complex system, if we have to figure out for each unit can be diverted to do the engineers. First of all, we look at 6443 platform, we are talking about is for the media player or media codecs. Because it is a system-on-chip SoC, it must have a main DSP processor system, the DSP is our improvement of the so-called C64x core 64. We have the 6416, the industry's top processor. BM642 also useful specialized processors, now with the first chip in the Da Vinci DM644x.
In addition, we have an ARM9 subsystem, many in the TI platform has a lot of applications, for example, DM320. The ARM9 is a 300-megabit. Leonardo da Vinci system in the addition of a VPSS subsystem, which has graphic overlay, but also can have video encoder, and can have 4 video output. In the peripheral areas, is very rich. We have a USB2.0 interface, where there are Ethernet interfaces, as well as a V (British) interface. This is the 6443 system, we need to remember the ARM subsystem, DSP subsystem, Video, there are all kinds of complicated interface.
Of 6446 for an increase of a system is the addition of a code, a CCD interface, as well as image zoom tool, as well as preview. These two together is the two-way subsystem 6446. Another is the VICP, if we understand the DM270, DM320, then it would be more familiar with. TI because it is the media treatment of a proprietary co-processor of the media. DM6446 is also a feature of the functional unit.
Through such a platform processors, we can now handle real-time H.264 SDTV, as well as MPEG-2, MPEG-4 decoder. We can also .264 BP D1 processing and coding as well as processing and encoding B264 BP CIF. The two chips for different markets, different platforms, different prices. Given the price we are in the market at a price can be.
Have just introduced is a platform, and now look at the Leonardo da Vinci which includes the software. First, from the bottom, we have the operating system and device drivers, we have MontaVista Linux LSP, as well as open-source Linux software. Aspects of multimedia application programming, we are also compatible with two, one is the industry's workers API interface, and is Leonardo da Vinci API, can provide customers with good software support. Other aspects such as middleware, codecs, extraction, inter-processor communications, audio / video framework for customers to build it. There are also various types of multimedia codecs, and as H.264, MPEG4, H.263, WMV9, VC1, MPEG2, JPEG. There are AAC, WMA9, WMA8. In addition to video and audio media in future, there are some aspects of voice, such as G.711, G.728, G.723.1, G.729ab, provided it is among the list of software.
If the domestic audio and video aspects of some new software standards can support? I would like to tell you that since Da Vinci is an open multimedia platform, support for new technologies is one of our support. Customers to authorize the development of TI.
Open programming environment, including such aspects, one is we have such an open platform for customers to open an open platform to do, SoC is very complex, for example, co-processor, such as a comprehensive development. The second link, we offer the industry's recognized as much as possible API, including video, audio, video and voice interface. We integrated development environment, as we integrated the 3.2, there are some new plug-ins contribute to the development of Leonardo da Vinci. In the development environment also provides a number of development frameworks, and management software, to OEM manufacturers, can be easily integrated multimedia codecs. First of all, we launched the TMS320DM6443 and TMS320DM6446 these two products, which is three months after we announced the launch of Da Vinci, we will have a series of DaVinci chips will be introduced.
DaVinci development tools, in the current release, the fact you can see the relevant information online, customers can place orders online. We look at our DaVinci development tools, hardware is a version that contains the contents of four aspects, first of all the hardware, the core chip is the DM6446, developed in order to facilitate the customers, but also contains some other very important parts, such as NTSC / PAL video camera, 5.6 inches LCD screen, speakers and microphone, IR remote control, hard disk drives (2.5-inch 40G). In terms of software includes a demo of the software can, for example, H.264, MPEM-4, MPEG-2, AAC +, G.711, multimedia API and framework, including support for plug-ins MontaVista2.6 10Linux. The connection has USB2.0 interface, 10/100EMAC, there are many other types of on-board memory, ComactFlash, ATA, SD, DDR. There are video interface NTSC / PAL. Through the NTSC / PAL & YPbPr / RGB video output, CD-level sound input and output, daughter card connected to the peripheral interface. Development tools and support, Linux development tools, high-speed video point of reference to guide the board design, DDR2 layout, where the layout of the corresponding DDR we have the appropriate guidance. Include this part of the Digital Video Evaluation Board, and now the price is not high, the price is equivalent to the introduction of the DM6442 evaluation board, but to provide content far beyond the original content.
The support of the Leonardo da Vinci, we will rely on a strong network of third-party support. Support for the TI, including the chip itself, as well as related information, as well as support for some hardware schematics. The second part is based on the strong third-party support, there will be there in video systems integration expertise to provide support. The third part is the product development for global support network. Here you can see, (slide) In addition to TI, there are a lot of partners, some provide software codec support, some provide real-time operating system, some provision of middleware, and some manufacturers is that we authorize the Duffing singular support of service providers.
Leonardo da Vinci the most prominent feature is a prominent efficiency, we make a comparison, for example, video in a typical development of these elements is inevitable, a real-time operating systems and device drivers, by the way the past 4-6 months, the framework of the system and application software support is likely to take 6-10 months, for the codec, for example, provide just the H.264, customers often need a year or so花到or more than one year. Also in the software and hardware development tools often need to close to a year's time. After the introduction of Da Vinci system, first of all, the most effective to shorten the time codec and hardware development, hardware reference video development platform provides us with the software has been rigorously tested software, it is possible to shorten the time to about a month or even less than a month. In the development of tools is the same, there is a very effective and efficient, customers do need to focus on the main characteristics of the system, they can in the system aspects of the framework API can also be unique in the system spent more energy. By Leonardo da Vinci developed this product, people will not lead to a phenomenon.
Products how to reduce the cost of Leonardo da Vinci? Through this plan can be an intuitive understanding of the current set-top boxes, video phones, digital surveillance systems have become increasingly demanding, in order to achieve some of the features on the need to achieve through the chip. In this system needs to use high-speed DSP, the need for more powerful control on the use of ARM, as the realization of picture-in-picture feature, USB interface, hard disk interface, video coding and decoding, the complexity of the video processing is necessary to use a different set of chip. Finally, the system will be high cost. Da Vinci used now, the impression you may also remember that we have the Da Vinci DSP, ARM, video co-processor, video subsystem, a lot of interfaces are integrated in a chip. For the system of 6446, we only need to spend less than the cost of 35 U.S. dollars, and the use of other chips may be required to spend 70 dollars. That is why the chip using the da Vinci system can save costs.
In fact we already have customers in the planning of their products, (slide) This is one of our customers, so it is the safety of single-channel network video platforms, such a platform only need to use a DM6446 DaVinci chip before they use very complicated to achieve MPGA control, need to achieve the USB controller CPLD, in a number of memory interface is also needed to achieve the FPGA, as well as external hardware needed CPLD接引need video The coding and decoding, also need to Ethernet interface. This is more complicated.
Now can see that Da Vinci used after 6446, many units have been no need, because many units have been included in the Leonardo da Vinci in. Only a very simple way to connect the corresponding peripheral equipment, as well as the necessary interface, analog video encoding, Ethernet physical layer interface, so it can constitute a new generation of low-cost products. Therefore, company executives said YMagic processor TMS320DM6446 seamless integration of video peripherals and accelerators to reduce the BOM cost of up to 30%. Due to further reduce BOM cost, system development time required for the corresponding reduction of the market is expected to be even earlier, to obtain a lower market price.
A final summing up, we can see (slide) Leonardo da Vinci is actually very important to deal with digital media technology, for some of the variety of innovative products, these products can be prepared in media players, Video security, set-top boxes, automotive infotainment systems, may have not yet planning, but it is very important that on the one hand, high resolution, as well as low-cost, there will be a lot of innovation in the future. The reason why there are so many innovations, we are through the use of third-party partners, that we will be planning more in the direction of new products.
